Title: Computer Methods for Circuit Analysis and Design / Edition 1, Author: Jirï Vlach
Title: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings / Edition 1, Author: Jorge Juan Chico
Title: A VHDL Synthesis Primer / Edition 2, Author: J. Bhasker
Title: VLSI Design for Manufacturing: Yield Enhancement / Edition 1, Author: Stephen W. Director
Title: Evolutionary Algorithms for VLSI CAD / Edition 1, Author: Rolf Drechsler
Title: Digital Systems Design Using VHDL / Edition 3, Author: Jr.
Title: Digital Design: Research and Practice / Edition 1, Author: Mao-Lin Chiu
Title: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation: 12th International Workshop, PATMOS 2002, Seville, Spain, September 11 - 13, 2002 / Edition 1, Author: Bertrand Hochet
Title: Correct Hardware Design and Verification Methods: IFIP WG10.5 Advanced Research Working Conference, CHARME '95, Frankfurt, Germany, October 1995. Proceedings / Edition 1, Author: Paolo Enrico Camurati
Title: VLSI: Systems on a Chip: IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99) December 1-4, 1999, Lisboa, Portugal / Edition 1, Author: Luis Miguel Silveira
Title: High-Level VLSI Synthesis / Edition 1, Author: Raul Camposano
Title: Correct Hardware Design and Verification Methods: 13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings / Edition 1, Author: Dominique Borrione
Title: Rapid Prototyping of Digital Systems: A Tutorial Approach / Edition 2, Author: James O. Hamblen
Title: Correct Hardware Design and Verification Methods: IFIP WG 10.2 Advanced Research Working Conference, CHARME'93, Arles, France, May 24-26, 1993. Proceedings / Edition 1, Author: George J. Milne
Title: Introduction to Analog VLSI Design Automation / Edition 1, Author: Mohammed Ismail
Title: Meta-Modeling: Performance and Information Modeling / Edition 1, Author: Jean-Michel Bergé
Title: Chapters in Architectural Drawing, Author: Daniel John Stine
Paperback from $36.35 $59.95 Current price is $36.35, Original price is $59.95.
Title: Verilog Coding for Logic Synthesis / Edition 1, Author: Weng Fook Lee
Title: Formal Equivalence Checking and Design Debugging / Edition 1, Author: Shi-Yu Huang
Title: Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design / Edition 1, Author: Fan Mo

Pagination Links