Advanced Formal Verification
Advanced Formal Verification shows the latest developments in the verification domain from the perspectives of the user and the developer. World leading experts describe the underlying methods of today's verification tools and describe various scenarios from industrial practice. In the first part of the book the core techniques of today's formal verification tools, such as SAT and BDDs are addressed. In addition, multipliers, which are known to be difficult, are studied. The second part gives insight in professional tools and the underlying methodology, such as property checking and assertion based verification. Finally, analog components have to be considered to cope with complete system on chip designs.

1116786160
Advanced Formal Verification
Advanced Formal Verification shows the latest developments in the verification domain from the perspectives of the user and the developer. World leading experts describe the underlying methods of today's verification tools and describe various scenarios from industrial practice. In the first part of the book the core techniques of today's formal verification tools, such as SAT and BDDs are addressed. In addition, multipliers, which are known to be difficult, are studied. The second part gives insight in professional tools and the underlying methodology, such as property checking and assertion based verification. Finally, analog components have to be considered to cope with complete system on chip designs.

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Advanced Formal Verification

Advanced Formal Verification

Advanced Formal Verification

Advanced Formal Verification

Overview

Advanced Formal Verification shows the latest developments in the verification domain from the perspectives of the user and the developer. World leading experts describe the underlying methods of today's verification tools and describe various scenarios from industrial practice. In the first part of the book the core techniques of today's formal verification tools, such as SAT and BDDs are addressed. In addition, multipliers, which are known to be difficult, are studied. The second part gives insight in professional tools and the underlying methodology, such as property checking and assertion based verification. Finally, analog components have to be considered to cope with complete system on chip designs.

Product Details

ISBN-13: 9781441954206
Publisher: Springer US
Publication date: 12/07/2010
Edition description: Softcover reprint of the original 1st ed. 2004
Pages: 250
Product dimensions: 6.10(w) x 9.25(h) x 0.24(d)

Table of Contents

What SAT-solvers Can and Cannot Do.- Advancements in Mixed BDD and SAT Techniques.- Equivalence Checking of Arithmetic Circuits.- Application of Property Checking and Underlying Techniques.- Assertion-Based Verification.- Formal Verification for Nonlinear Analog Systems: Approaches to Model and Equivalence Checking.
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