Advanced Semiconductor Memories: Architectures, Designs, and Applications / Edition 1

by Ashok K. Sharma

Overview

A valuable reference for the most vital microelectronic components in the marketplace

DRAMs are the technology drivers of high volume semiconductor fabrication processes for new generation products that, in addition to computer markets, are finding increased usage in automotive, aviation, military and space, telecommunications, and wireless industries. A new generation of high-density and high-performance memory architectures evolving for mass storage devices, including embedded memories and nonvolatile flash memories, are serving a diverse range of applications.

Comprehensive and up to date, Advanced Semiconductor Memories: Architectures, Designs, and Applications offers professionals in the semiconductor and related industries an in-depth review of advanced semiconductor memories technology developments. It provides details on:

• Static Random Access Memory technologies including advanced architectures, low voltage SRAMs, fast SRAMs, SOI SRAMs, and specialty SRAMs (multiport, FIFOs, CAMs)
• High Performance Dynamic Random Access Memory-DDRs, synchronous DRAM/SGRAM features and architectures, EDRAM, CDRAM, Gigabit DRAM scaling issues and architectures, multilevel storage DRAMs, and SOI DRAMs
• Applications-specific DRAM architectures and designs - VRAMs, DDR SGRAMs, RDRAMs, SLDRAMs, 3-D RAM
• Advanced Nonvolatile Memory designs and technologies, including floating gate cell theory, EEPROM/flash memory cell design, and multilevel flash
• FRAMs and reliability issues
• Embedded memory designs and applications, including cache, merged processor, DRAM architectures, memory cards, and multimedia applications
• Future memory directions with megabytes to terabytes storage capacities using RTDs, single electron memories, etc.

A continuation of the topics introduced in Semiconductor Memories: Technology, Testing, and Reliability, the author's earlier work, Advanced Semiconductor Memories: Architectures, Designs, and Applications offers a much-needed reference to the major developments and future directions of advanced semiconductor memory technology.

Product Details

ISBN-13:	9780471208136
Publisher:	Wiley
Publication date:	10/14/2002
Pages:	672
Product dimensions:	6.30(w) x 9.30(h) x 1.70(d)

About the Author

ASHOK K. SHARMA is the author of Semiconductor Memories: Technology, Testing, and Reliability (Wiley-IEEE Press, 1997). He is currently working as a reliability engineering manager at NASA, Goddard Space Flight Center, Greenbelt, Maryland.

Read an Excerpt

Advanced Semiconductor Memories

Architectures, Designs, and Applications

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By Ashok K. Sharma

John Wiley & Sons

ISBN: 0-471-20813-2

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Chapter One

INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES

1.1. SEMICONDUCTOR MEMORIES OVERVIEW

The goal of Advanced Semiconductor Memories is to complement the material already covered in Semiconductor Memories. The earlier book covered the following topics: random access memory technologies (SRAMs and DRAMs) and their application to specific architectures; nonvolatile technologies such as the read-only memories (ROMs), programmable read-only memories (PROMs), and erasable PROMs in both ultraviolet erasable (UVPROM) and electrically erasable (EEPROM) versions; memory fault modeling and testing; memory design for testability and fault tolerance; semiconductor memory reliability; semiconductor memories radiation effects; advanced memory technologies; and high-density memory packaging technologies. This section provides a general overview of the semiconductor memories topics that are covered in Semiconductor Memories.

In the last three decades of semiconductor memories' phenomenal growth, the DRAMs have been the largest volume volatile memory produced for use as main computer memories because of their high density and low cost per bit advantage. SRAM densities have generally lagged a generation behind the DRAM. However, the SRAMs offer low-power consumption and high-performance features, which makes them practical alternatives to the DRAMs. Nowadays, a vast majority of SRAMs are being fabricated in the NMOS and CMOS technologies (and a combination of two technologies, also referred to as the mixed-MOS) for commodity SRAMs.

In 1995, semiconductor memories accounted for 42% of the total IC market, but following 1995's strong growth, memory prices collapsed for the next three years. In 1998, memory devices represented only 21% of the total IC market. During the 1990s, semiconductor memory sales averaged approximately 30% of total IC sales. It is forecasted that the memory portion of total IC sales will gradually increase through year 2005. Figure 1.1 shows the semiconductor memory market as a percentage of the total IC market.

In high-density and high-speed applications, various combinations of bipolar and MOS technologies are being used. In addition to MOS and bipolar memories, referred to as the "bulk silicon" technologies, silicon-on-insulator (SOI) isolation technologies have been developed for improved radiation hardness.

SRAM density and performance are usually enhanced by scaling down the device geometries. Advanced SRAM designs and architectures for 4 to 16-Mb chips with submicron feature sizes have been developed and currently available as commodity chips. Application-specific memory designs include first-in-first-out (FIFO) buffer memory, in which the data are transferred in and out serially. The dual-port RAMs allow two independent devices to have simultaneous read and write access to the same memory. The content addressable memories (CAMs) are designed and used both as the embedded modules on larger VLSI chips, and as stand-alone memory for specific system applications.

A major improvement in DRAM evolution has been the switch from three-transistor (3T) designs to one-transistor (IT) cell design, enabling production of 4- to 16-Mb density chips that use advanced 3-D trench capacitor and stacked capacitor cell structure. Currently, 64-Mb to 1-Gb DRAM chips are in production, and multigigabit density chips are being developed. The technical advances in multimegabit DRAMs have resulted in greater demand for application-specific products such as the pseudostatic DRAM (PSRAM), which uses dynamic storage cells but contains all refresh logic on-chip that enables it to function similarly to an SRAM. Video DRAMs (VDRAMs) have been produced for use as the multiport graphic buffers. Some other examples of high-speed DRAM innovative architectures are synchronous DRAMs (SDRAMs), cache DRAMs (CDRAMs), and Rambus[TM] DRAMs (RDRAMs).

Nonvolatile memories (NVMs) have also experienced tremendous growth since the introduction in 1970 of a floating polysilicon gate-based erasable program read-only memory (EPROM), in which hot electrons are injected into the floating gate and removed either by ultraviolet internal photoemission or by Fowler-Nordheim tunneling. The EPROMs (also referred to as the UVEPROMs) are erased by removing them from the target system and exposing them to ultraviolet light. An alternative to EPROM (or UVEPROM) has been the development of electrically erasable PROMs (EEPROMs), which offer in-circuit programming flexibility. Several variations of this technology include metal-nitride-oxide-semiconductor (MNOS), silicon-oxide-nitrideoxide-semiconductor (SONOS), floating gate tunneling oxide (FLOTOX), and textured polysilicon. The FLOTOX is most commonly used EEPROM technology. An interesting NVM architecture is the nonvolatile SRAM, a combination of EEPROM and SRAM in which each SRAM has a corresponding "shadow" EEPROM cell.

Flash memories based on EPROM or EEPROM technologies are devices for which contents of all memory array cells can be erased simultaneously, unlike the EEPROMs that have select transistors incorporated in each cell to allow for the individual byte erasure. Therefore, the flash memories can be made roughly two or three times smaller than the floating gate EEPROM cells. Flash memories are available in 8- to 512-Mb densities as production devices, and even higher densities in development.

DRAMs are currently (and predicted to be in the future) the largest memory segment in terms of dollar sales. After DRAMs the SRAMs and flash markets represent the next two largest memory segments. In year 2000, the flash memory market surpassed the SRAM market and became the second-largest memory market segment. Both DRAM and flash market shares are expected to continue growing through 2005, although flash memory at a much faster pace. The remaining memory segments are predicted to remain stable.

Figure 1.2a shows a comparison of different MOS technologies market share projected to year 2005. It is predicted that in year 2005, the DRAMs will account for just 60% of the memory market, whereas flash memory sales is forecast to account for 29% of the total memory market. Figure 2.2b shows percentages for each MOS memory technology market for the year 2000 and predicted values for the year 2005.

Semiconductor Memories reviewed various memory failure modes and mechanisms, fault modeling, and electrical testing. A most commonly used fault model is the single-stuck-at fault (SSF), which is also referred to as the classical standard fault model. However, many other fault models have also been developed for transition faults (TFs), address faults (AFs), bridging faults (BFs), coupling faults (CFs), pattern-sensitive faults (PSFs), and the dynamic (or delay) faults. A large percentage of physical faults occurring in the ICs can be considered as the bridging faults (BFs), consisting of shorts between the two or more cells or lines. Another important category of faults that can cause the RAM cell to function erroneously is the coupling or PSFs.

In general, the memory electrical testing consists of the dc and ac parametric tests and functional tests. For RAMs, various functional test algorithms have been developed for which the test time is a function of the number of memory bits (n) and range in complexity from O(n) to O([n.sup.2]). The selection of a particular set of test patterns for a given RAM is influenced by the type of failure modes to be detected, memory bit density that influences the test time, and the memory automated test equipment (ATE) availability.

Advanced megabit memory architectures are being designed with special test features to reduce the test time by the use of multibit test (MBT), line mode test (LMT), and built-in self-test (BIST). Application-specific memories such as the FIFOs, video RAMs, synchronous static and dynamic RAMs, and double-buffered memories (DBMs) have complex timing requirements and multiple setup modes that require a suitable mix of sophisticated test hardware, design for testability (DFT), and BIST approach.

In general, the memory testability is a function of variables such as circuit complexity and design methodology. Therefore, the DFT techniques, RAM and ROM BIST architectures, memory error detection and correction (EDAC), and the memory fault tolerance are important design considerations. Structured design techniques are based upon the concept of providing uniform design to increase controllability and observability. The commonly used methodologies include the level-sensitive scan design (LSSD), scan path, scan/set logic, random access scan, and the boundary scan testing (BST). The RAM BIST implementation strategies include the use of algorithmic test sequence (ATS), the 13-N March algorithms with a data-retention test, a fault-syndrome-based strategy for detecting the PSFs, and built-in logic block observation (BILBO) technique. For the embedded memories, various DFT and BIST techniques have been developed such as the scan-path-based flag-scan register (FLSR) and the random-pattern-based circular self-test path (CSTP). Advanced BIST architectures have been implemented to allow parallel testing with on-chip test circuits. The current generation megabit memory chips include spare row and columns (redundancies) in the memory array to compensate for the fault cells. In addtion, to improve the memory chip yield, techniques such as built-in self-diagnosis (BISD) and built-in self-repair (BISR) are used.

The errors in semiconductor memories can be broadly categorized as the hard failures caused permanent physical damage to the device and soft errors caused by alpha particles or the ionizing dose radiation environments. The most commonly used error-correcting codes (ECC) that are used to correct hard and soft errors are the single-error correction and double-error detection (SEC-DED) codes, also referred to as the Hamming Codes. Multimegabit DRAM chips have been developed that use redundant word and bit lines in conjunction with ECC to produce optimized fault tolerance effect. To recover from the soft errors (transient effects), memory scrubbing techniques are often used, which are based upon the probabilistic or deterministic models. These techniques can be used to calculate the reliability rate R(t) and mean time to failure (MTTF) of the memory system.

Semiconductor Memories reviewed general reliability issues for semiconductor devices such as the memories, RAM failure modes and mechanisms, nonvolatile memory reliability, reliability modeling and failure rate prediction, design for reliability, and reliability test structures. The general reliability issues pertaining to semiconductor devices in bipolar and MOS technologies are applicable to memories also. In addition, there are special reliability issues and failure modes, which are of special concern for the RAMs. These issues include gate oxide reliability defects, hot-carrier degradation, the DRAM capacitor charge-storage and data-retention properties, and DRAM soft-error failures. The memory gate dielectric integrity and reliability are affected by all processes involved in the gate oxide growth.

The reduced MOS transistor geometries from scaling of the memory devices has made them more susceptible to hot-carrier degradation effects. Nonvolatile memories, just like volatile memories, are also susceptible to some specific failure mechanisms. In the floating gate technologies such as the EPROM and EEPROMs, data retention characteristics and number of write/erase cycles without degradation (endurance) are the most critical reliability concerns.

Reliability failure modeling is the key to the failure rate prediction, and there are many statistical distributions that are used to model various reliability parameters. The method of accelerated stress aging for semiconductor devices such as memories is commonly used to ensure long-term reliability. An approach commonly used by the memory manufacturers in conjunction with the end-of-line product testing has been the use of reliability test structures and process (or yield) monitors incorporated at the wafer level and "drop-in" test sites on the chip. The purpose of reliability testing is to quantify the expected failure of a device at various points in its life cycle.

The space radiation environment poses a certain radiation risk to all electronic components on earth-orbiting satellites and the planetary mission spacecrafts. The cumulative effect of ionization damage from charged particles present in the natural space environment, such as the electrons and protons on semiconductor memories, can be significant. Ionizing radiation damage causes changes in memory circuit parameters such as standby power supply currents, I/O voltage threshold levels and leakage currents, critical path delays, and timing specification degradations. The single-event phenomenon (SEP) in the memories is caused by high-energy particles such as those present in the cosmic rays passing through the device to cause (a) single-event upsets (SEUs) or soft errors and (b) single-event latchup (SEL), which may result in hard errors. The impact of SEU on the memories, because of their shrinking dimensions and increasing densities, has become a significant reliability concern. The nonvolatile MOS memories are also subject to radiation degradation effects.

The memory circuits can be designed for total dose radiation hardness by using optimized processes (e.g., hardened gate oxides and field oxides) and good design practices. The bulk CMOS memories have been hardened to SEU by using an appropriate combination of processes and design techniques. Radiation sensitivity of unhardened memory devices can vary from lot to lot; and for space applications, radiation testing is required to characterize the lot radiation tolerance. Semiconductor Memories discussed the following topics in detail: radiation-hardening techniques, radiation-hardening design issues, radiation testing, radiation dosimetry, wafer level testing, and test structures.

Advanced semiconductor memories technologies include ferroelectric RAMs (FRAMs or FeRAMs), magnetoresistive RAMs (MRAMs), analog memories, and quantum-mechanical switch memories. These technologies were briefly reviewed in Semiconductor Memories.

The increasing requirements for denser memories have led to further compaction of standard packaging approach to hybrid manufacturing techniques and multichip modules (MCMs). For the assembly of MCMs, various interconnect technologies have been developed such as the wire-bonding, tape automated bonding (TAB), flip-chip bonding, and high-density interconnect (HDI). An extension of 2-D planar technology has been the 3-D concept, in which the memory chips are mounted vertically prior to the attachment of a suitable interconnect. The 3-D approach can provide higher packaging densities because of (a) reduction in the substrate size, module weight, and volume, (b) lower line capacitance and drive requirements, and (c) reduced signal propagation delay times. Semiconductor Memories reviewed commonly used memory packages, memory hybrids and 2-D MCMs, memory stacks and 3-D MCMs, memory MCM testing and reliability issues, memory cards, and high-density memory packaging future directions.

1.2. ADVANCED SEMICONDUCTOR MEMORY DEVELOPMENTS

This book, Advanced Semiconductor Memories, reviews in detail future advances in SRAMs, high-performance DRAMs, application-specific DRAM designs and architectures, nonvolatile memory technologies, embedded memory designs and applications, and future gigabit-to-terabit memory directions. These advanced developments are briefly summarized in this section.

Advanced SRAM technology developments are reviewed in Chapter 2. SRAMs are currently available for both asynchronous and synchronous designs in a wide variety of speeds and architectures. However, synchronous designs are preferred and use one or more external clock signals to control the SRAM operations, and they result in improved timing controls. This allows the reduction of the device access times and cycle times to match the clock cycles of the fastest PC and RISC processors available. The synchronous SRAM (SSRAM) data buses are usually flow-through or pipelined. In the communication networks, SRAMs are being used as data buffers between the input and output ports, and they are also being used as high-speed lookup tables containing addresses and other information to route data stream from the data source to destination.

(Continues...)

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Table of Contents

PREFACE xix

1 INTRODUCTION TO ADVANCED SEMICONDUCTOR MEMORIES 1

1.1. Semiconductor Memories Overview 1

1.2. Advanced Semiconductor Memory Developments 8

1.3. Future Memory Directions 16

References 18

2 STATIC RANDOM ACCESS MEMORY TECHNOLOGIES 19

2.1. Basic SRAM Architecture and Cell Structures 19

2.1.1. SRAM Performance and Timing Specifications 21

2.1.2. SRAM ReadWrite Operations 23

2.2. SRAM Selection Considerations 26

2.3. High Performance SRAMs 33

2.3.1. Synchronous SRAMs Flow-Through 41

2.3.2. Zero Bus Turnaround SRAMs 43

2.3.3. Quad Data Rate SRAM 44

2.3.4. Double Data Rate SRAM 50

2.3.5. No-Turnaround Random Access Memory 51

2.4. Advanced SRAM Architectures 55

2.5. Low-Voltage SRAMs 61

2.6. BiCMOS Technology SRAMs 75

2.7. SOI SRAMs 79

2.8. Specialty SRAMs 91

2.8.1. Multiport RAMs 92

2.8.1.1. Dual-Port RAMs 92

2.8.1.2. Quadport™ RAMs 101

2.8.2. First-In-First-Out (FIFO) Memories 103

2.8.3. Content Addressable Memories (CAMs) 111

2.8.3.1. Advanced Content Addressable Memories (Examples) 116

References 122

3 HIGH-PERFORMANCE DYNAMIC RANDOM ACCESS MEMORIES 129

3.1. DRAM Technology Evolution and Trends 129

3.2. DRAM Timing Specifications and Operations 133

3.2.1. General Timing Specifications 133

3.2.2. Memory Read Operation 135

3.2.3. Memory Write Operation 138

3.2.4. Read-Modify-Write Operation 140

3.2.5. DRAM Refresh Operation 141

3.3. Extended-Data-Out DRAMS 145

3.3.1. EDO DRAM (Example) 145

3.4. Enhanced DRAM (EDRAM) 146

3.5. Synchronous DRAMGRAM Architectures 150

3.5.1. SDR SDRAMSGRAM 150

3.5.2. DDR SDRAMSGRAM Features 151

3.5.3. Synchronous DRAM 256Mb (Example) 154

3.5.3.1. Initialization 154

3.5.3.2. Register Definition 155

3.5.3.3. Commands 157

3.5.3.4. SDRAM Operations 159

3.6. Enhanced Synchronous DRAM (ESDRAM) 163

3.7. Cache DRAM (CDRAM) 166

3.8. Virtual Channel Memory (VCM) DRAMs 172

3.9. Advaned DRAM Technology Perspectives 175

3.9.1. Memory Capacitor Cell Improvements 179

3.9.2. 64-Mb DRAMs 188

3.9.3. 256-Mb DRAMs 195

3.10. Gigabit DRAM Scaling Issues and Architectures 200

3.11. Multilevel Storage DRAMs 217

3.12. SOI DRAMs 221

References 231

4 APPLICATION-SPECIFIC DRAM ARCHITECTURES AND DESIGNS 237

4.1. Video RAMs (VRAMs) 241

4.2. Synchronous Graphic RAMs (SGRAMs) 244

4.2.1. 64-Mb DDR SGRAM 246

4.2.2. 256-Mb DDR Fast Cycle RAM 253

4.3. Rambus Technology Overview 257

4.3.1. Direct RDRAM Technologies and Architectures 264

4.3.2. Direct Rambus Memory System-Based Designs 272

4.4. Synchronous Link DRAMs (SLDRAMs) 275

4.4.1. SLDRAM Standard 277

4.4.2. SLDRAM Architectural and Functional Overview 283

4.4.3. SLDRAM (Example) 285

4.5. 3-D RAM 296

4.5.1. Pixel ALU Operations 305

4.6. Memory System Design Considerations 309

References 316

5 ADVANCED NONVOLATILE MEMORY DESIGNS AND TECHNOLOGIES 319

5.1. Nonvolatile Memory Advances 319

5.1.1. Introduction 319

5.1.2. Serial EEPROMs 323

5.1.3. Flash Memory Developments 327

5.2. Floating Gate Cell Theory and Operations 334

5.2.1. Floating Gate Cell Theory 334

5.2.2. Charge Transport Mechanisms 339

5.2.2.1. Fowler-Nordheim Tunneling 340

5.2.2.2. Polyoxide Conduction 342

5.2.2.3. Channel Hot-Electron Injection (CHEI) 343

5.2.2.4. Direct Band-to-Band Tunneling 347

5.3. Nonvolatile Memory Cell and Array Designs 350

5.3.1. UV-EPROM (or EPROM) Cells 350

5.3.1.1. T-Cell EPROM 351

5.3.1.2. X-Cell EPROM 351

5.3.1.3. Staggered Virtual Ground (SVG) Cell Array EPROM 352

5.3.1.4. Alternate Metal Virtual Ground (AMG) Cell Array EPROM 353

5.3.2. EEPROM Cells 354

5.3.3. Flash Memory Cells 354

5.3.3.1. T-Cell Flash 355

5.3.3.2. Alternate Metal Ground (AMG) Flash Cell 357

5.3.3.3. Source-Coupled Split-Gate (SCSG) Flash Cell 358

5.3.3.4. Field-Enhancing Tunneling Injector Flash Cell 359

5.3.3.5. Triple-Polysilicon Virtual Ground (TPVG) Flash Cell 362

5.3.3.6. Divided Bit-Line NOR (DINOR) Flash Cell 363

5.3.3.7. AND Flash Cell 365

5.3.3.8. High Capacitive Coupling Ratio (HiCr) Flash Cell 366

5.3.3.9. NAND Flash Cell 366

5.3.4. Flash Memory Cell Basic Operation and Processes 368

5.3.5. Flash EEPROM Technology Developments 372

5.4. Flash Memory Architectures 377

5.4.1. NOR Flash Memories 378

5.4.1.1. AMD NOR Architecture Flash Memories 381

5.4.1.2. Intel Flash Memories 387

5.4.2. NAND Flash Memories 392

5.4.2.1. AMD NAND Architecture Flash Memories 393

5.4.2.2. Samsung 32M x 8-bit NAND Architecture Flash Memory 397

5.4.2.3. Virtual DRAM 401

5.4.3. DINOR Architecture Flash Memories 403

5.4.3.1. A 16-Mb DINOR Flash Memory 405

5.4.3.2. P-Channel DINOR Flash Memory 406

5.4.3.3. BiNOR Cell Flash Memory 408

5.4.4. AND Architecture Flash Memories 410

5.4.5. Specialty Flash Memories 411

5.5. Multilevel Nonvolatile Memories 412

5.5.1. Multilevel NOR Flash Memories 418

5.5.2. Multilevel NAND Flash Memories 426

5.5.2.1. A 512-Mb NAND Flash Memory 429

5.5.3. Multilevel AND Flash Memories 429

5.6. Flash Memory Reliability Issues 430

5.6.1. General Failure Mechanisms for EPROMsEEPROMs 430

5.6.1.1. Stuck Bit 434

5.6.1.2. Data Retention Degradation 434

5.6.1.3. Read Time Degradation 434

5.6.1.4. Erase Time Degradation 434

5.6.1.5. Program Time Degradation 434

5.6.1.6. Disturbs 434

5.6.2. Flash Memory Reliability 435

5.6.2.1. Flash Overerase 436

5.6.2.2. Flash Program Disturbs 436

5.6.2.3. Flash Read Disturbs 437

5.6.2.4. Flash ProgramErase Endurance 437

5.6.2.5. Flash Data Retention Failures 439

5.6.2.6. Flash Hot Carrier Reliability Effects 441

5.6.2.7. Multilevel Flash Reliability 442

5.7. Ferroelectric Memories 443

5.7.1. Technology Overview 443

5.7.2. Ferroelectric Materials and Memory Design 451

5.7.3. Megabit FRAMs 454

5.7.4. Chain FRAM (CFRAM) 463

5.7.5. Metal Ferroelectric Semiconductor FET 465

5.7.6. FRAM Reliability Issues 467

References 469

6 EMBEDDED MEMORIES DESIGNS AND APPLICATIONS 479

6.1. Embedded Memory Developments 479

6.2. Cache Memory Designs 487

6.2.1. Cache Architecture Implementation for a DSP (Example) 495

6.3. Embedded SRAMDRAM Designs 499

6.3.1. Embedded SRAM Macros 503

6.3.1.1. A IT SRAM Macro 504

6.3.1.2. A 4T SRAM Macro 506

6.3.2. Embedded DRAM Macros 508

6.3.2.1. dRAMASICs 508

6.3.2.2. A Compiled 100-MHz DRAM Macro 509

6.3.2.3. A Dual-Port Interleaved DRAM Architecture Macro 511

6.3.2.4. A 1-GHz Synchronous DRAM Macro 513

6.4. Merged Processor DRAM Architectures 516

6.5. DRAM Processes with Embedded Logic Architectures 522

6.5.1. A Modular Embedded DRAM Core 523

6.5.2. Multimedia Accelerator with Embedded DRAM 524

6.5.3. Intelligent RAM (IRAM) 527

6.5.4. Computational RAM 530

6.6. Embedded EEPROM and Flash Memories 533

6.7. Memory Cards and MultiMedia Applications 536

6.7.1. Memory Cards 536

6.7.2. Single-Chip Flash Disk 544

References 547

7 FUTURE MEMORY DIRECTIONS: MEGABYTES TO TERABYTES 549

7.1. Future Memory Developments 549

7.2. Magnetoresistive Random Access Memories (MRAMs) 551

7.2.1. MRAM Technology Developments and Tradeoffs 551

7.2.2. MRAM Cells and Architectures 556

7.2.3. 256K1-Mb GMRAMs 566

7.2.4. Multilevel MRAMs 571

7.3. Resonant Tunneling Diode-Based Memories 572

7.3.1. Resonant Tuneling Diode Theory 572

7.3.2. Tunneling SRAM (TSRAM) Cell Designs 574

7.3.3. RTD-Based Memory System (Example) 579

7.4. Single-Electron Memories 582

7.4.1. Single-Electron Device Theory 582

7.4.2. Single-Electron Memory Characteristics and Configurations 590

7.4.3. Single-Electron Devices Fabrication Techniques 595

7.4.4. Nanocrystal Memory Devices 596

7.5. Phase-Change Nonvolatile Memories 602

7.6. Protonic Nonvolatile Memories 607

7.7. Miscellaneous Memory Technology Development (Examples) 612

7.7.1. Thyristor-Based SRAM Cell (T-RAM) 613

7.7.2. Content Addressable Read-Only Memory (CAROM) 614

7.7.3. Nanotech Memories 618

7.7.4. Solid-State Holographic Memories 618

References 623

INDEX 631