Architecture-Aware Optimization Strategies in Real-time Image Processing / Edition 1

Architecture-Aware Optimization Strategies in Real-time Image Processing / Edition 1

ISBN-10:
178630094X
ISBN-13:
9781786300942
Pub. Date:
11/29/2017
Publisher:
Wiley
ISBN-10:
178630094X
ISBN-13:
9781786300942
Pub. Date:
11/29/2017
Publisher:
Wiley
Architecture-Aware Optimization Strategies in Real-time Image Processing / Edition 1

Architecture-Aware Optimization Strategies in Real-time Image Processing / Edition 1

$177.95
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Overview

In the field of image processing, many applications require real-time execution, particularly those in the domains of medicine, robotics and transmission, to name but a few. Recent technological developments have allowed for the integration of more complex algorithms with large data volume into embedded systems, in turn producing a series of new sophisticated electronic architectures at affordable prices.  This book performs an in-depth survey on this topic. It is primarily written for those who are familiar with the basics of image processing and want to implement the target processing design using different electronic platforms for computing acceleration.  The authors present techniques and approaches, step by step, through illustrative examples. This book is also suitable for electronics/embedded systems engineers who want to consider image processing applications as sufficient imaging algorithm details are given to facilitate their understanding.


Product Details

ISBN-13: 9781786300942
Publisher: Wiley
Publication date: 11/29/2017
Pages: 192
Product dimensions: 6.30(w) x 9.40(h) x 0.30(d)

About the Author

Chao Li, Chinese Academy of Sciences, China.

Souleymane Balla-Arabe, CNRS, France.

Fan Yang, University of Burgundy, France.

Read an Excerpt

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Table of Contents

1. Introduction of Real-time Image Processing.

2. Hardware Architectures forReal-time Processing.

3. Rapid Prototyping of Parallel Reconfigurable Instruction Set Processor for Efficient Real-Time Image Processing.

4. Exploration of High-Level Synthesis Technique.

5. CDMS4HLS: A Novel Source- To-SourceCompilation Strategy for HLS-Based FPGA Design.

6. Embedded Implementation of VHR Satellite Image Segmentation.

7. Real-time Image Processing with Very High-level Synthesis.

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