CMOS Data Converters for Communications / Edition 1 available in Hardcover
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CMOS Data Converters for Communications / Edition 1
- ISBN-10:
- 079237780X
- ISBN-13:
- 9780792377801
- Pub. Date:
- 01/31/2000
- Publisher:
- Springer US
- ISBN-10:
- 079237780X
- ISBN-13:
- 9780792377801
- Pub. Date:
- 01/31/2000
- Publisher:
- Springer US
![CMOS Data Converters for Communications / Edition 1](http://img.images-bn.com/static/redesign/srcs/images/grey-box.png?v11.10.4)
CMOS Data Converters for Communications / Edition 1
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Overview
Product Details
ISBN-13: | 9780792377801 |
---|---|
Publisher: | Springer US |
Publication date: | 01/31/2000 |
Series: | The Springer International Series in Engineering and Computer Science , #543 |
Edition description: | 2000 |
Pages: | 378 |
Product dimensions: | 6.10(w) x 9.25(h) x 0.36(d) |
Read an Excerpt
Chapter 4: Overview of D/a Converter architectures
IntroductionIn this chapter we present different techniques for converting a digital signal into an analog signal representation. The approaches differ in speed, chip area, power efficiency, achievable accuracy, etc. It is therefore necessary to understand which converter algorithms or architectures to choose for the specific application. For example, when the conversion bandwidth is relatively small, it could be advantageous to use a higher sampling ratio and some oversampling technique to reduce the noise energy within the signal band. If very high speeds are required, a flash converter architecture should be used. However, the trade-off in converter design is normally between resolution and bandwidth (or the update frequency over signal frequency ratio). The higher bandwidth the lower resolution is generally achievable.
In Sec. 4.2 we discuss the concept of Nyquist-rate conversion, and in Sec. 4.3 to Sec. 4.8 we show different implementations for Nyquist-rate DaCs. There is a limited number of DaC architectures that are good candidates for high-speed and high-performance applications. One is the current-steering DaC, which uses a number of binary scaled elements which generate the output value.
In Sec. 4.9, we discuss the concept of oversampling D/a conversion. In this book we refer to an oversampling DaC (OSDaC) to a converter operating at a higher update frequency and also containing a noise shaping loop. Often, the OSDaC utilizes some kind of a Nyquist-rate converter (with a lower nominal resolution) together with digital modulators and analog filters.
To further increase the performance of DaCs, some special enhancement techniques can be used, as for example dynamic randomization and dynamic element matching (DEM) techniques. This is discussed in Sec. 4.10.
In Sec. 4.11 we compare a number of DaC architectures reported in the literature and in data sheets from vendors. We present an overview of the performance in terms of linearity vs. update and signal frequencies.
Nyquist Rate D/a Converters
In general the Nyquist-rate converter is required for wide band applications where oversampling techniques are impossible due to the high clocking frequency. In for example, audio applications an oversampling D/a converter (OSDaC) is preferred. Since a Nyquist-rate converter also is used in most OSDaCs we first present some general and common Nyquist-rate DaC architectures. We discuss application areas and highlight some of the advantages and disadvantages with the different types of converter architectures. The architectures that are discussed, are the binary weighted, thermometer coded, and encoded DaC architectures. The different architectures can be combined into hybrid DaCs where the advantages of different individual architectures are used.
We are considering DaCs for telecommunication applications and therefore we focus on candidates suitable for high speed and high resolution. However, lower-speed DaCs such as the algorithmic DaC are also briefly presented. These lower-speed DaCs can be used in pipeline DaCs where the throughput is increased by pipelining.
To illustrate the principle of the DaC, usually single-ended circuits are used. In a real implementation they are differential circuits to improve linearity and SNR. In this chapter, we consider only binary offset coded inputs. To represent a negative output of the converter, the reference elements of the most significant bit get the opposite sign, i.e., a 2's complement coded input.
We use three modes of circuit technology; voltage-mode, current-mode, and chargeredistribution mode. We associate voltage-mode with a DaC where the element values are given by voltage levels as for example in a resistor-string which divides a voltage reference level into a number of different amplitude levels. With current-mode the DaC elements are currents, as for example switched current sources or resistors dividing a major current into weighted subcurrents. Finally, charge-redistribution DaCs are using the switched-capacitor technique (SC). Note that the SC technique usually is refered to as a voltage-mode technique as well...