Digital Hardware Testing

by Rochit Rajsuman

Overview

Digital Hardware Testing presents realistic transistor-level fault models and testing methods for all types of circuits. The discussion details design-for-testability and built-in self-test methods, with coverage of boundary scan and emerging technologies such as partial scan, cross check, and circular self-test-path.

Product Details

ISBN-13:	9780890065808
Publisher:	Artech House, Incorporated
Publication date:	12/01/1992
Series:	Artech House Telecommunications Library Series
Pages:	340
Product dimensions:	6.00(w) x 9.00(h) x 0.88(d)

Table of Contents

	Preface	xiii
Chapter 1	Introduction to Digital IC Testing	1
1.1	Introduction	1
1.2	Testing Problem and Considerations	2
1.3	Computational Complexity of Testing Problem	3
1.4	Estimation of Difficulty in Controllability and Observability	4
1.5	Summary	8
	Problems	8
References8
Chapter 2	Faults in Digital Circuits	9
2.1	Introduction	9
2.2	General VLSI Fault Models	10
2.2.1	Stuck-at Fault Model	10
2.2.2	Bridging and Open Fault Model	11
2.2.3	Fault Equivalence, Dominance, and Collapsing	13
2.2.4	Parametric and Transient Faults	14
2.2.5	Delay Fault Models	14
2.3	Specific Fault Models	15
2.3.1	PLA Fault Model	15
2.3.2	Memory Fault Model	16
2.3.3	Microprocessor Fault Model	17
2.4	Summary	18
	Problems	18
	References	19
Chapter 3	Bridging Faults in Random Logic	21
3.1	Introduction	21
3.2	Characterization of Bridging Faults	21
3.3	Bridging within a Logic Element	22
3.4	Bridging of Logical Nodes without Feedback	25
3.5	Bridging of Logical Nodes with Feedback	33
3.6	Bridging in Dynamic Gates	37
3.6.1	CMOS Domino Logic	38
3.6.2	Cascade Voltage Switch Logic	40
3.6.3	Clocked CMOS Logic	40
3.7	Effect of Substrate Connection	42
3.8	Summary	49
	Problems	50
	References	51
Chapter 4	Open Faults in Random Logic	53
4.1	Introduction	53
4.2	Modeling of Open Faults	53
4.3	Problems in Testing Open Faults	55
4.3.1	Test Invalidation by Timing Skews	55
4.3.2	Test Invalidation by Charge Distribution	57
4.3.3	Test Invalidation Due to Glitches	57
4.4	Methods to Test Stuck-Open Faults	59
4.4.1	Robust Test Sequences	59
4.4.2	Testable Designs	60
4.5	Testability of Dynamic Circuits	67
4.6	Summary	68
	Problems	68
	References	69
Chapter 5	Test Generation and Fault Simulation	71
5.1	Introduction	71
5.2	Test Generation at Gate Level	71
5.2.1	Boolean Difference Method	72
5.2.2	Path Sensitization and D-Algorithm	75
5.2.3	Algorithm PODEM	78
5.2.4	Algorithm FAN	79
5.3	Fault Coverage by a Test	82
5.3.1	Critical Path Tracing	83
5.3.2	Multiple Faults	87
5.4	Random Test Generation	89
5.5	Test Generation at Switch Level	93
5.6	Fault Simulation	96
5.7	Summary	98
	Problems	99
	References	99
Chapter 6	Testing of Structured Designs (PLAs)	101
6.1	Introduction	101
6.2	Structure of a PLA	101
6.3	Easily Testable PLA	105
6.3.1	PLA Testing with Parity Trees	105
6.3.2	Universal Test Set for Easily Testable PLAs	106
6.3.3	Variations of Parity-Based Testable Design	109
6.4	Built-in Self-Test PLA	111
6.5	Testing of EEPLA	111
6.6	Testing for Multiple Faults in PLA	116
6.7	Fault Isolation and Reconfiguration	119
6.8	Summary	120
	Problems	122
	References	122
Chapter 7	Testing of Random Access Memory	123
7.1	Introduction	123
7.2	Test Algorithms	123
7.2.1	Algorithm GALPAT	124
7.2.2	Checker Pattern Test	124
7.2.3	Galloping Diagonal/Row/Column Test	125
7.2.4	Marching 1/0 Test Algorithm	126
7.2.5	Modified Marching 1/0 Test	126
7.2.6	Comparison and Modification for Word-Oriented Memory	127
7.3	Testable Designs	129
7.3.1	BIST Memory	130
7.3.2	Memory Partitioning Methods	131
7.3.3	STD Architecture	134
7.4	Fault Diagnosis and Reconfiguration	138
7.5	Advantages and Disadvantages	139
7.6	Summary	142
	Problems	142
	References	143
Chapter 8	Testing of Sequential Circuits	145
8.1	Introduction	145
8.2	Testing Problem in Sequential Circuits	145
8.3	State Table Approach	146
8.3.1	Initialization of Sequential Circuits	146
8.3.2	State Table Verification	151
8.4	Gate Level Test Generation Methods	152
8.4.1	Sequential Test Generation by Boolean Difference	153
8.4.2	Iterative Logic Array Model	155
8.4.3	Simulation-Based Test Generation	164
8.4.4	Divide and Conquer	166
8.5	Synthesis for Testability	170
8.6	Summary	171
	Problems	172
	References	173
Chapter 9	Microprocessor Testing	175
9.1	Introduction	175
9.2	Microprocessor Description and Testing	175
9.3	Instruction Set Verification	176
9.3.1	Machine-Level Verification	176
9.3.2	Microinstruction-Level Verification	182
9.4	Bit-Sliced Microprocessors	186
9.4.1	Testing of One-Bit Slice	187
9.4.2	Testing of k-Bit Processor	189
9.5	Concurrent Checking	191
9.5.1	Error-Detecting Codes	192
9.5.2	Check-Point Technique	192
9.5.3	Watchdog Processor	194
9.6	Summary	194
	References	195
Chapter 10	Design for Testability	197
10.1	Introduction	197
10.2	SCAN Design	197
10.2.1	Multiplexed Data Scan Design	198
10.2.2	Level Sensitive Scan Design	200
10.2.3	Pros and Cons	203
10.3	Partial SCAN	204
10.4	Boundary SCAN	207
10.4.1	Basic Concept	207
10.4.2	Test Access Port	209
10.5	Cross-Check Design	212
10.6	Built-in Self-Test	216
10.7	Test Pattern Generators	217
10.7.1	Deterministic Test Pattern Generators	217
10.7.2	Pseudorandom Test Vectors	217
10.7.3	Pseudoexhaustive	222
10.8	Response Compression for BIST	223
10.8.1	Parity Testing	224
10.8.2	One-Count Testing	224
10.8.3	Syndrome Testing	225
10.8.4	Transition Count	226
10.8.5	Signature Analysis	227
10.9	BIST Test Structures	232
10.9.1	Built-in Logic Block Observer (BILBO)	232
10.9.2	Self-Test Using MISRs and Parallel SRSGs (STUMPS)	233
10.9.3	Circular Self-Test Path	234
10.10	Summary	235
	Problems	236
	References	237
Chapter 11	Current Testing	239
11.1	Introduction	239
11.2	Basic Concept	239
11.3	Estimation of Fault-Free Current	244
11.3.1	Current Through a Single Gate	244
11.3.2	Estimation of Current in a Circuit	247
11.4	Current Sensing Techniques	249
11.4.1	External Current Sensor	249
11.4.2	Built-in Current Sensor	252
11.5	Test Generation for IDDQ Testing	254
11.6	Summary	257
	Problems	260
	References	260
Chapter 12	Reliability Testing	263
12.1	Introduction	263
12.2	Component Quality and Fault Coverage	264
12.3	Reliability and Failure Rate	265
12.4	Failure Mechanisms	269
12.4.1	Chip Related Failures	269
12.4.2	Assembly Related Failures	271
12.4.3	Operation Induced Failures	273
12.4.4	Application Induced Failures	279
12.5	Reliability Test Methods	281
12.6	Accelerated Reliability Testing	282
12.6.1	Temperature Acceleration	285
12.6.2	Current Acceleration	287
12.6.3	Voltage Acceleration	288
12.6.4	Temperature-Humidity Acceleration	290
12.6.5	Vibration and Shock Acceleration	291
12.6.6	Temperature, Humidity, and Power Cycling	291
12.7	Burn-in	292
12.8	Testing of Application Induced Failures	293
12.9	Summary	294
	Problems	294
	References	294
	Appendix A	297
A.1	Error Models	297
A.2	Computation of Aliasing Probability	298
Appendix B	Annotated Bibliography	303
	Index	311

Editorial Reviews

A guide to testing integrated circuits for defects arising from the manufacturing process. After a thorough discussion of fault models and the complexity of the testing problem, describes the testing of combinational and sequential circuits, and current testing, a topic rarely covered elsewhere. Based on the proposition that the most effective and economical approach is to construct a fault model for each circuit, then test for the particular defects that are most likely. Annotation c. Book News, Inc., Portland, OR (booknews.com)

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