Future Trends in Microelectronics: Reflections on the Road to Nanotechnology / Edition 1

by S. Luryi, Jimmy Xu, Alex Zaslavsky

Overview

Silicon technology has developed along virtually one single line: reducing the minimal size of lithographic features. But has this taken us to the point of diminishing returns? Are we now at a turning point in the logical evolution of microelectronics? Some believe that the semiconductor microelectronics industry has matured: the research game is over (comparisons with the steel industry are being made). Others believe that qualitative progress in hardware technology will come roaring back, based on innovative research.
This debate, spirited as it is, is reflected in the pages of Future Trends in Microelectronics, where such questions are discussed. What kind of research does the silicon industry need to continue its expansion? What is the technical limit to shrinking Si devices? Is there any economic sense in pursuing this limit? What are the most attractive applications of optoelectronic hybrid systems? Are there any green pastures beyond the traditional semiconductor technologies? Identifying the scenario for the future evolution of microelectronics will present a tremendous opportunity for constructive action today.

Product Details

ISBN-13:	9780792341697
Publisher:	Springer Netherlands
Publication date:	08/31/1996
Series:	NATO Science Series E: , #323
Edition description:	1996
Pages:	422
Product dimensions:	6.14(w) x 9.21(h) x 0.36(d)

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Future Trends in Microelectronics Reflections on the Road to Nanotechnology

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By Serge Luryi Springer

Copyright © 1996 Serge Luryi
All right reserved.
ISBN: 9780792341697

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Chapter One

Microelectronics Technology: Challenges in the 21st Century

S. M. Sze National Nano Device Laboratory National Chiao Tung University, Hsinchu, Taiwan, R.O.C.

1. Introduction

The earliest semiconductor device was the metal-semiconductor contact studied in 1874 to reveal that the resistance of a contact between a metal and a semiconductor depends on the magnitude and polarity of the applied voltage. The earliest technology related to semiconductor processing was the lithography technique invented in 1798. In this process, the pattern, or image, was transferred from a stone plate (litho).

In the past two centuries, the most important milestones in semiconductor development were the inventions of the bipolar transistor in 1947 and the integrated circuit in 1959. The bipolar transistor ushered in the modern electronics era and the integrated circuit laid the foundation for the rapid growth of the microelectronics industry. In the past four decades, there has been phenomenal progress in microelectronics technology and enormous expansion of the global semiconductor market. The electronics industry has grown to be the largest in the world with global sales of over one trillion dollars. The foundation of the electronicsindustry is microelectronics technology.

Figure 1 shows the sales volume of the semiconductor-device-based electronics industry in the past 20 years and projects sales to the year 2010. Also shown are the gross world product (GWP) and the sales of the automobile, steel, and semiconductor industries. Electronics industry sales surpassed automobile industry sales in 1998. If the current trends continue, in year 2010 the sales volume of the electronics industry will constitute about 4.5% of the GWP. The semiconductor industry will grow even faster, to surpass the steel industry in the early 21st century and to constitute 30% of the electronics industry in 2010.

We shall review the key achievements in the past four decades and consider some major challenges we face in the 21st century. These challenges include:

the growth of super-large wafers, the sub-100-nm resolution of lithography systems,

the ultra-small dimensions of logic and memory devices,

the parasitic RC delay of multi-level interconnect, and

the huge capital investment of the microelectronics industry.

We must develop innovative technologies and new products to meet these challenges and to move successfully toward the nanoelectronic era. If we succeed, it is predicted that by the year 2030, the semiconductor industry and the electronics industry may reach 3 trillion dollars and 10 trillion dollars in sales, respectively.

2. Key achievements

Since 1959, we have had many achievements in the microelectronics industry. Of particular significance were:

1. the developments of DRAM (1967), the nonvolatile semiconductor memory (1967), and the microprocessor (1971);

2. phenomenal progress in design and process technology with a 190 times reduction in minimum feature length and four million times increase in DRAM density; and

3. the enormous expansion of the global market with a 400 times increase in sales volume and a 50 billion times increase in annual shipments of transistors.

This progress is summarized in Table 1. Also shown in the table are the increase in Si wafer diameter by a factor of twelve, the 2x[10.sup.4] times increase in microprocessor clock rate, the 5x[l0.sup.5] times increase in nonvolatile memory density, and over [10.sup.7] times decrease in average transistor price. If the automobile industry could achieve the same kind of progress as the microelectronics industry, a Rolls Royce would cost only 25 cents, get over 3,000,000 miles per gallon of gas, and could deliver enough power to drive the Queen Elizabeth II ocean liner. No other industries in human history have had such an enormous impact on the global economy and society so quickly.

Figure 2 shows the density of DRAM chips in the past 20 years and projects the density to the year 2010. Figure 3 shows the microprocessor computational power (in million instructions per second or MIPS) over the same period. We note that both DRAM density and microprocessor power increase exponentially with time, doubling every 18 months, or a factor of four every 3 years - the well-known Moore's Law.

Table 2 shows the International Technology Roadmap for Semiconductors based on Moore's Law. For example, in year 2010 the DRAM chip area will be increased to 14 [cm.sup.2], the minimum feature length will be scaled to 50 nm, and the cost per transistor will be reduced to 10 microcent.

The main concern we have is how long can Moore's Law remain valid - that is, how long can the microelectronics industry maintain its historical rate of performance and cost improvement? There are many challenges we face in the 21st century. We shall consider some major challenges in the next section.

3. Major challenges

We shall consider five major challenges: wafer, lithography, device, interconnect, and economy.

The first major challenge is super-large-diameter wafers. Figure 4 shows silicon wafer diameter and ingot weight in the past 50 years and projects to the year 2010. We note that since the mid-1950's, the wafer diameter has increased exponentially, doubling every 12 years. The most advanced process lines have already adopted 300-mm (12-inch) wafers. Figure 5 shows a 300-mm diameter ingot (left) and a 400-mm diameter ingot. It is very difficult to grow such large-diameter ingots, because the weight of the ingot is over 200 kg for 300 mm wafers and 350 kg for 400 mm wafers. In addition, special arrangements (such as movable magnetic coils) are needed to damp thermal convection for the large volume of melt in the Czochralski crystal growth. Also we have to eliminate the crystal-originated pits (COPs), which are voids with diameters of 10-100 nm. For 200-mm wafers the density of COPs is typically [10.sup.5] [cm.sup.-3]. However, for 300-mm wafers, complete elimination of COPs is necessary for acceptable device yield.

Table 3 compares production costs for 200-mm and 300-mm wafers. Consider the case of a wafer with copper metalization, a low-[kappa] interlayer dielectric, and a 0.13-?m design rule. There is a 57% increase in cost per wafer when we go from 200- to 300-mm wafers, however, the cost per unit area for the 300 mm wafer is 30% lower. Therefore, 300-mm and even larger diameter wafers will be used as long as the production cost per unit area can be reduced. If an epitaxial layer of 2-3 ?m is required, there will be additional cost for the epi process. For 300-mm wafers, we require a thickness tolerance of ? 4% and a density of structural defects of less than 0.002 defects per [cm.sup.2]; even tighter controls are needed for larger wafers.

The second major challenge is lithography systems with sub-100-nm resolution. It is expected that the 193-nm ArF laser projection lithography system will support the 100-nm technology node, using resolution enhancement techniques such as phase-shifting masks (PSMs) and optical proximity correction (OPC). For even smaller design rules, there are five possible lithography tools, as shown in Fig. 6.

The 157-nm [F.sub.2] laser projection lithography system is a strong candidate for the 70-nm technology node. Electron-beam projection systems, such as SCALPEL (scattering with angular limitation projection electron-beam lithography), are limited by electron proximity effects. X-ray lithography systems are limited by mask fabrication complexities. Ion-beam systems are limited by stochastic space-charge effects. The most likely candidate for sub-70-nm technology nodes is the extreme ultraviolet (EUV) system with a wavelength of 13 nm. The EUV system potentially is capable of providing resolutions down to 20 nm with high wafer throughput. To produce such EUV systems before the year 2005, we need close international collaboration and a tight development schedule.

The third major challenge is ultra-small devices for logic and memory applications. Currently, the dominant logic device is the MOSFET. Figure 7 shows the evolution of MOSFET architecture. The conventional MOSFET structure can be scaled down to 70 nm. For even smaller devices, an SOI (silicon-on-insulator) substrate or pulse doping may be needed. Eventually a dualgate structure may be needed. We also can envision a lithography-independent process with a vertical structure by turning the device 90?. Recently, an experimental MOSFET with a 20-nm gate length has been demonstrated, illustrated in Fig. 8. The gate oxide thickness is only 0.8 nm. The transconductance is very high, over 1200 mS/mm for nMOS and 700 mS/mm for pMOS. The gate delay is very short, less than 0.8 ps for nMOS and 1.7 ps for pMOS. These results indicate that the MOSFET will remain the key device for logic circuits for the foreseeable future.

At present, the dominant memory devices are the DRAM (mainly for office equipment) and the nonvolatile semiconductor memory (NVSM such as flash memory, mainly for portable systems). The highest density for DRAMs is probably around 64 Gbit because it becomes very difficult to control the amount of charge in the storage capacitor at this density. The most likely candidate for high-density memory beyond 64 Gbit is the single-electron memory cell (SEMC). The SEMC is a limiting case of NVSM, as shown in Fig. 9(b). When we reduce the floating gate of a conventional NVSM, Fig. 9(a), to an ultra-small floating dot (~10 nm), the capacitance of the floating dot is very small, on the order of 0.1-1 aF ([10.sup.-l9]-[10.sup.-18] F) range. When an electron tunnels into the quantum well of the floating dot, the potential in the well will increase to block the entrance of another electron - the Coulomb blockade. Figure 10 shows the density of SEMC vs. the minimum feature length. Room-temperature operation of a 265-Tbit (250x[10.sup.12] bits) SEMC is projected for a minimum feature length of 1 nm.

To fabricate ULSI circuits with ultra-small devices, we need extensive material innovations, such as silicon-on-insulator substrates (e.g. the smart-cut method using hydrogen implantation), high-dielectric materials (e.g. barium strontium titanate and [Ta.sub.2][O.sub.5]) for DRAM, low-dielectric materials for interlayer isolation (e.g. black diamond and fluorinated amorphous carbon), and highly electromigration-resistant materials for metalization (e.g. copper).

The fourth major challenge is the parasitic RC delay due to interconnects. As we continue to reduce the minimum feature length and increase the circuit complexity, both the parasitic resistance and capacitance increase. At the sub-100-nm technology node, the interconnect parasitic RC delay becomes orders of magnitude larger than the intrinsic gate delay.

To minimize the RC delay, multilevel interconnect schemes have been developed with copper replacing aluminum to improve the electromigration performance. A six-level damascene copper interconnect for a 180-nm design rule is shown in Fig. 11. For even smaller design rules, 8 or more levels are required. Another approach to minimum RC delays is to develop system-on-chip ICs.

An elegant method to solve the interconnect problem is silicon microphotonics. For such an approach, we need three photonic components to take care of photon creation, photon propagation, and photon detection. On the left side of Fig. 12 we show a possible means for photon creation by employing the silicon-erbium LED. The photon propagation can be accomplished easily by using on-chip Si/Si[O.sub.2] optical fiber; since the refractive index ratio is quite large (3.5/1.5), the LED output will be confined in the silicon core region. For photon detection, we can use a SiGe alloy as shown on the right side of Fig. 12. The responsivity is quite high over a wide range of wavelengths (e.g. higher than 0.3 A/W from 1080 ntn to 1520 nm). If the silicon microphotonic approach can be successfully implemented, we can substantially reduce RC delays, provide precise clock distribution and system synchronization, reduce power dissipation, improve voltage isolation and impedance matching, and minimize cross-talk and pin inductance.

The fifth major challenge is economy. We need low-cost manufacturing and new applications to broaden the electronics market. The cost per fab line has doubled every 3 years. In 1995, the cost of a fab line was about $750 million; now it is $3 billion; in ten years, it will cost $24 billion. We have to find ways to reduce the fab-line cost and to improve its productivity and yield.

Based on Fig. 1, we have extrapolated the GWP, electronics sales, and semiconductor sales to the year 2040, as shown in Fig. 13. If we assume that the GWP will maintain its current annual growth rate of 3% in the next 40 years, it will reach $100 trillion in 2030, and $134 trillion in 2040. If the electronics industry can maintain its current 7% annual growth rate, it will reach $10 trillion in 2030, i.e., 10% of the GWP. It is unlikely that any one industry can constitute more than 10% of the GWP. Therefore, after 2030 the electronics sales will level off, and increase at the same ~3% rate as the GWP.

The global semiconductor industry will most likely maintain its current high growth rate of 14% to the year 2010. By then, semiconductor sales will reach $800 billion to constitute about 30% of electronics sales. This ratio is probably an upper limit for semiconductor sales because there are many other components in an electronic system such as the software, display, and packaging.

Therefore, after 2010, the growth rate of semiconductor sales will be reduced to 7%, and after 2030 it will be further reduced to 3%. However, in the event that electronics sales reach beyond 10% of the GWP and that semiconductor sales go beyond 30% of electronics sales, the semiconductor industry would enjoy a higher than 7% growth rate after 2010, and a higher than 3% growth rate after 2030.

4. Conclusion

In the past 40 years, microelectronics has been responsible for the rapid growth of the global electronics industry, which is now the largest industry in the world ( > $1 trillion). There are many major challenges in microelectronics: large wafers, sub-100-nm lithography, ultra-small devices, interconnect, and economic challenges.

We believe that super-large-diameter wafers will be adopted as long as the production cost per unit wafer area can be reduced. For lithography, the 157-nm [F.sub.2] system will most likely be used for the 70-nm technology node, and EUV for the 50-nm and even smaller technology nodes. The dominant logic device will continue to be the MOSFET, and the dominant memory device will be the single-electron memory cell - the ultimate floating-gate nonvolatile semiconductor memory.

Integrated-circuit performance will be limited by interconnect. An elegant solution is silicon microphotonics, since all the required photonic components are readily available. We need low-cost manufacturing processes and broadened electronics markets to maintain the growth of the microelectronics industry. We expect that the global electronics industry will reach $10 trillion in the year 2030. However, we must develop innovative microelectronic and nanoelectronic technologies to meet the aforementioned challenges.

Continues...

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Excerpted from Future Trends in Microelectronics Reflections on the Road to Nanotechnology by Serge Luryi Copyright © 1996 by Serge Luryi. Excerpted by permission.
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Table of Contents

Usli Microelectronics: Challenges and Future Directions.- All that Glitters isn’t Silicon Or Steel and Aluminum Re-Visited.- Si-Microelectronics: Perspectives, Risks, Opportunities, Challenges — 12 Statements.- Mass Production of Nanometre Devices.- Active Packaging: a New Fabrication Principle for High Performance Devices and Systems.- The Wiring Challenge: Complexity and Crowding.- Physics, Materials Science, and Trends in Microelectronics.- Growing up in the shadow of a Silicon ‘older brother’; tales of an abusive childhood from GaAs and other new technology siblings!.- Comments on the National Technology Roadmap for Semiconductors.- System and Architecture Evolutions and Device Limitations.- Critique of reversible computation and other energy saving techniques in future computational systems.- Architectural Frontiers Enabled by High Connectivity Packaging.- Processor Performance Scaling.- Nano and Quantum Electronics.- Quantum Devices for Future CSICs.- Challenges and Trends for the Application of Quantum-Based Devices.- Wire and dot related devices.- Nonlithographic Fabrication and Physics of Nanowire and Nanodot Array Devices — Present and Future.- Taming Tunneling En Route to Mastering Mesoscopics.- Prospects for Quantum Dot Structures Applications in Electronics and Optoelectronics.- Architectures for Nano-scaled Devices.- Simulations and Modeling.- Simulating Electronic Transport in Semiconductor Nanostructures.- Monte Carlo Simulation for Reliability Physics Modeling and Prediction of Scaled (100 NM) Silicon MOSFET Devices.- New Materials and Device Technologies.- Superconductor-Semiconductor Devices.- Field Effect Transistor as Electronic Flute.- Heterodimensional Technology for Ultra Low Power Electronics.- Lateral Current Injection Lasers — ANew Enabling Technology for OEICs.- Wide Band Gap Semiconductors. Good Results and Great Expectations.- GaN and Related Compounds for Wide Bandgap Applications.- Prospects in Wide-Gap Semiconductor Lasers.- Organic Transistors — Present and Future.- Microcavity Emitters and Detectors.- Optical Amplification, Lasing and Wavelength Division Multiplexing Integrated in Glass Waveguides.- Systems and Circuits.- Ultimate Performance of Diode Lasers in Future High-Speed Optical Communication Systems.- Increased-functionality VLSI-compatible Devices Based on Backward-diode Floating-base Si/SiGe Heterojunction Bipolar Transistors.- Real-Space-Transfer of Electrons in the InGaAs/InAlAs System.- Charge Injection Transistor and Logic Elements in Si/Si1-xGex Heterostructures.- New Ideology of All-Optical Microwave Systems Based on the Use of Semiconductor Laser as a Down-Converter.- Microtechnology — Thermal Problems in Micromachines, ULSI and Microsensors Design.- Emerging and Future Intelligent Aviation and Automotive Applications of MIMO ASIM Microcommutators and ASIC Microcontrollers.- Trends in Thermal Management of Microcircuits.- Contributors.