Logic Synthesis and Verification Algorithms / Edition 1

by Gary D. Hachtel

Overview

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students.

Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics.

A unique feature of this text is the large collection of solved problems.

Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs.

Product Details

ISBN-13:	2900387310045
Publisher:	Springer US
Publication date:	02/10/2006
Edition description:	1996
Pages:	564
Product dimensions:	6.00(w) x 1.25(h) x 9.00(d)

Table of Contents

I: Introduction.
1. Introduction.
2. A Quick Tour of Logic Synthesis with the Help of a Simple Example.
II: Two Level Logic Synthesis.
3. Boolean Algebras.
4. Synthesis of Two-Level Circuits.
5. Heuristic Minimization of Two-Level Circuits.
6. Binary Decision Diagrams (BDDs)
III: Models of Sequential Systems.
7. Models ofSequential Systems.
8. Synthesis and Verification of Finite State Machines.
9. Finite Automata.
IV: Multilevel Logic Synthesis.
10. Multi-Level Logic Synthesis.
11. Multi-Level Minimization.
12. Automatic Test Generation for Combinational Circuits.
13. Technology Mapping.
A. ASCII Codes.
B. Supplementary Problems.
Bibliography.
Index.