Network Processor Design: Issues and Practices, Volume 3 / Edition 3 available in Paperback
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Network Processor Design: Issues and Practices, Volume 3 / Edition 3
- ISBN-10:
- 0120884763
- ISBN-13:
- 9780120884766
- Pub. Date:
- 02/15/2005
- Publisher:
- Elsevier Science
- ISBN-10:
- 0120884763
- ISBN-13:
- 9780120884766
- Pub. Date:
- 02/15/2005
- Publisher:
- Elsevier Science
![Network Processor Design: Issues and Practices, Volume 3 / Edition 3](http://img.images-bn.com/static/redesign/srcs/images/grey-box.png?v11.9.4)
Network Processor Design: Issues and Practices, Volume 3 / Edition 3
Paperback
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$94.95Overview
Through chapters on hardware, software, performance and modeling, Network Processor Design illustrates the potential for new NP applications, helping to lay a theoretical foundation for the architecture, evaluation, and programming of networking processors.
Like Volume 2 of the series, Volume 3 further shifts the focus from achieving higher levels of packet processing performance to addressing other critical factors such as ease of programming, application developments, power, and performance prediction. In addition, Volume 3 emphasizes forward-looking, leading-edge research in the areas of architecture, tools and techniques, and applications such as high-speed intrusion detection and prevention system design, and the implementation of new interconnect standards.
- Investigates current applications of network processor technology at Intel; Infineon Technologies; and NetModule
- Presents current research in network processor design in three distinct areas:
- Architecture at Washington University, St. Louis; Oregon Health and Science University; University of Georgia; and North Carolina State University.
- Tools and Techniques at University of Texas, Austin; Academy of Sciences, China; University of Paderborn, Germany; and University of Massachusetts, Amherst.
- Applications at University of California, Berkeley; Universidad Complutense de Madrid, Spain; ETH Zurich, Switzerland; Georgia Institute of Technology; Vrije Universiteit, the Netherlands; and Universiteit Leiden, the Netherlands.
Product Details
ISBN-13: | 9780120884766 |
---|---|
Publisher: | Elsevier Science |
Publication date: | 02/15/2005 |
Series: | Morgan Kaufmann Series in Computer Architecture and Design Series , #3 |
Pages: | 336 |
Product dimensions: | 0.70(w) x 7.50(h) x 9.25(d) |
About the Author
Haldun Hadimioglu received his BS and MS degrees in Electrical Engineering at Middle East Technical University, Ankara Turkey and his Ph.D. in Computer Science from Polytechnic University in New York. He is currently an Industry Associate Professor in the Computer Science Department and a member of the Computer Engineering faculty at the Polytechnic University. He worked as a research engineer at PETAS, Ankara Turkey (1980-1982). Dr. Hadimioglu's research and teaching interests include Computer Architecture, Parallel and Distributed Systems, Networking and VLSI Design. He was a guest editor of the special issue on "Advances in High Performance Memory Systems," IEEE Transactions on Computers (Nov 2001) and has reviewed papers for leading journals such as the IEEE Transactions on Computers. Hadimioglu is a member of the IEEE, the ACM, and Sigma Xi. He has been an organizer of various workshops including, the ISCA Memory Wall (2000), ISCA Memory Performance Issues (2002, 2001) and HPCA8 Workshop on Network Processors (2002). He received Dedicated Faculty and Outstanding Faculty awards from Polytechnic students in 1995 and 1993, respectively.
Peter Z. Onufryk received his B.S.E.E. from Rutgers University, M.S.E.E. from Purdue University, and Ph.D. in Electrical and Computer Engineering from Rutgers University. He is currently a director in the Internetworking Products Division at Integrated Device Technology, Inc. where he is responsible for architecture definition and validation of communications products. Before joining IDT, Peter was a researcher for thirteen years at AT&T Labs - Research (formally AT&T Bell Labs) where he worked on communications systems and parallel computer architectures. These included a number of parallel, cache-coherent multiprocessor and dataflow based machines that were targeted towards high performance military systems. Other work there focused on packet telephony and early network processors. Onufryk is a member of the IEEE. He was an organizer and program committee member of the HPCA8 Workshop on Network Processors 2002. Peter was the architect of four communications processors as well as numerous ASICs, boards, and systems.
Read an Excerpt
The latest information from the leading network processor designers in research and industry.
Table of Contents
1. Network Processors: New HorizonsPatrick Crowley, Mark A. Franklin, Haldun Hadimioglu, Peter Z. Onufryk
2. Supporting Mixed Real-Time Workloads in
Multithreaded Processors with Segmented
Instruction Caches
Patrick Crowley
3. Efficient Packet Classification with Digest Caches
Francis Chang, Wu-chang Feng, Wu-chi Feng, Kang Li
4 Towards a Flexible Network Processor Interface for
RapidIO, Hypertransport, and PCI-Express
Christian Sauer, Matthias Gries, Kurt Keutzer, Jose Ignacio Gomez
5. A High-Speed, Multithreaded TCP Offload Engine for 10 Gb/s Ethernet
Yatin Hoskote, Sriram Vangal, Vasantha Erraguntla, Nitin Borkar
6. A Hardware Platform for Network Intrusion Detection and Prevention
Chris Clark,Wenke Lee, David Schimmel, Didier Contis, Mohamed Koné, Ashley Thomas
7. Packet Processing on a SIMD Stream Processor
Jathin S. Rai, Yu-Kuen Lai, Gregory T. Byrd
8. A Programming Environment for Packet-Processing
Systems: Design Considerations
Harrick Vin, Jayaram Mudigonda, Jamie Jason, Erik J. Johnson,Roy Ju, Aaron Kunze, Ruiqi Lian
9. RNOSA Middleware Platform for Low-Cost
Packet-Processing Devices
Jonas Greutert, Lothar Thiele
10. On the Feasibility of Using Network Processors for DNA Queries
Herbert Bos, Kaiming Huang
11. Pipeline Task Scheduling on Network Processors
Mark A. Franklin, Seema Datar
12. A Framework for Design Space Exploration of Resource Efficient Network Processing on Multiprocessor SoCs
Matthias Grünewald, Jörg-Christian Niemann, Mario Porrmann, Ulrich Rückert
13. Application Analysis and Resource Mapping for Heterogeneous Network Processor Architectures
Ramaswamy Ramaswamy, Ning Weng, Tilman Wolf
References
Index