Skew-Tolerant Circuit Design / Edition 1

by David Harris

Overview

As advances in technology and circuit design boost operating frequencies of microprocessors, DSPs and other fast chips, new design challenges continue to emerge. One of the major performance limitations in today's chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Increasing clock frequencies are forcing many engineers to rethink their timing budgets and to use skew-tolerant circuit techniques for both domino and static circuits. While senior designers have long developed their own techniques for reducing the sequencing overhead of domino circuits, this knowledge has routinely been protected as trade secret and has rarely been shared. Skew-Tolerant Circuit Design presents a systematic way of achieving the same goal and puts it in the hands of all designers.This book clearly presents skew-tolerant techniques and shows how they address the challenges of clocking, latching, and clock skew. It provides the practicing circuit designer with a clearly detailed tutorial and an insightful summary of the most recent literature on these critical clock skew issues.

Product Details

ISBN-13:	9781558606364
Publisher:	Elsevier Science
Publication date:	05/22/2000
Series:	The Morgan Kaufmann Series in Computer Architecture and Design
Edition description:	New Edition
Pages:	300
Product dimensions:	7.38(w) x 9.25(h) x (d)

About the Author

David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons.

Table of Contents

Chapter 1 - Introduction Chapter 2 - Fundamental Concepts Chapter 3 - IP Switching Chapter 4 - Tag Switching Chapter 5 - MPLS Core Protocols Chapter 6 - Quality of Service Chapter 7 - Constraint­based routing Chapter 8 - Virtual Private Networks

Editorial Reviews

"Harris leads the way to more performance with a clear strategy for design. He shows how to combine logic and latching to do more logic in less time. In an era where less stuff means higher speed, everyone interested in high performance logic must understand these techniques or be left behind."—Ivan Sutherland, Vice President and Fellow, Sun Microsystems"The author thoroughly explains important circuit design techniques including various types of latch design styles, clocking strategies, and methods of accounting for clock skew. That all of this is captured in one place is one of the great strengths of this book."—Emily J. Shriver, Alpha Development Group, Compaq Computer Corporation

From the Publisher