Software and Compilers for Embedded Systems: 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings / Edition 1

by Andreas Krall

Overview

This volume contains the proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2003, held in Vienna, Austria, September 24–26, 2003. Initially, the workshop was referred to as the International Workshop on Code Generation for Embedded Systems. The first workshop took place in 1994 in Schloss Dagstuhl, Germany. From its beg- nings, the intention of the organizers was to create an atmosphere in which the researcherscould participateactively in dynamic discussionsand profit from the assembly of international experts in the field. It was at the fourth workshop, in St. Goar, Germany, in 1999, that the spectrum of topics of interest for the workshop was extended, and not only code generation, but also software and compilers for embedded systems, were considered. The change in fields of interest led to a change of name, and this is when the present name was used for the first time. Since then, SCOPES has been held again in St. Goar, Germany, in 2001; Berlin, Germany, in 2002; and this year, 2003, in Vienna, Austria. In response to the call for papers, 43 very strong papers from all over the world were submitted. The program committee selected 26 papers for pres- tation at SCOPES 2003. All submitted papers were reviewed by at least three experts in order to ensure the quality of the work presented at the workshop.

Product Details

ISBN-13:	9783540201458
Publisher:	Springer Berlin Heidelberg
Publication date:	11/05/2003
Series:	Lecture Notes in Computer Science , #2826
Edition description:	2003
Pages:	406
Product dimensions:	6.10(w) x 9.17(h) x 0.03(d)

Table of Contents

Invited Talk.- The Transmeta Crusoe: VLIW Embedded in CISC.- Code Size Reduction.- Limited Address Range Architecture for Reducing Code Size in Embedded Processors.- Predicated Instructions for Code Compaction.- Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation.- Code Selection.- Code Instruction Selection Based on SSA-Graphs.- A Code Selection Method for SIMD Processors with PACK Instructions.- Reconstructing Control Flow from Predicated Assembly Code.- Loop Optimizations.- Control Flow Analysis for Recursion Removal.- An Unfolding-Based Loop Optimization Technique.- Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer.- Automatic Retargeting.- Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation.- Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models.- System Design.- A Framework for the Design and Validation of Efficient Fail-Safe Fault-Tolerant Programs.- A Case Study on a Component-Based System and Its Configuration.- Composable Code Generation for Model-Based Development.- Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor.- Register Allocation.- Retargetable Graph-Coloring Register Allocation for Irregular Architectures.- Fine-Grain Register Allocation Based on a Global Spill Costs Analysis.- Offset Assignment.- Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment.- Improving Offset Assignment through Simultaneous Variable Coalescing.- Analysis and Profiling.- Transformation of Meta-Information by Abstract Co-interpretation.- Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java.- Towards Superinstructions for Java Interpreters.- Memory and Cache Optimizations.- Partitioning for DSP Software Synthesis.- Efficient Variable Allocation to Dual Memory Banks of DSPs.- Cache Behavior Modeling of Codes with Data-Dependent Conditionals.- FICO: A Fast Instruction Cache Optimizer.