Verification by Error Modeling: Using Testing Techniques in Hardware Verification / Edition 1

by Katarzyna Radecka, Zeljko Zilic

Overview

1. DESIGN FLOW Integrated circuit (IC) complexity is steadily increasing. ICs incorporating hundreds of millions of transistors, mega-bit memories, complicated pipelined structures, etc., are now in high demand. For example, Intel Itanium II processor contains more than 200 million transistors, including a 3 MB third level cache. A billion transistor IC was said to be “imminently doable” by Intel fellow J. Crawford at Microprocessor Forum in October 2002 [40]. Obviously, designing such complex circuits poses real challenges to engineers. Certainly, no relief comes from the competitive marketplace, with increasing demands for a very narrow window of time (time-to-market) in engineering a ready product. Therefore, a systematic and well-structured approach to designing ICs is a must. Although there are no widely adhered standards for a design flow, most companies have their own established practices, which they follow closely for in-house design processes. In general, however, a typical product cycle includes few milestones. An idea for a new product starts usually from an - depth market analysis of customer needs. Once a window of opportunity is found, product requirements are carefully specified. Ideally, these parameters would not change during the design process. In practice, initial phases of preparing a design specification are susceptible to potential errors, as it is very difficult to grasp all the details in a complex design.

Product Details

ISBN-13:	9781402076527
Publisher:	Springer US
Publication date:	11/30/2003
Series:	Frontiers in Electronic Testing , #25
Edition description:	2003
Pages:	216
Product dimensions:	6.10(w) x 9.25(h) x 0.02(d)

Table of Contents

Boolean Function Representations.- Don’t Cares and Their Calculation.- Testing.- Design Error Models.- Design Verification by At.- Identifying Redundant Gate and Wire Replacements.- Conclusions and Future Work.

Editorial Reviews

From the reviews:

"This monograph presents, as its main contribution, methods to gain more confidence in verification by simulation. … The methods presented in this book may be suitable to verify gate level circuits which may have small modifications after automatic optimization or some manual interaction." (Reiner Kolla, Zentralblatt MATH, Vol. 1049 (24), 2004)

From the Publisher