VHDL Coding Styles and Methodologies

VHDL Coding Styles and Methodologies

by Ben Cohen
VHDL Coding Styles and Methodologies

VHDL Coding Styles and Methodologies

by Ben Cohen

Paperback(Softcover reprint of the original 1st ed. 1995)

$54.99 
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Overview

VHDL Coding Styles and Methodologies was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy to read book that gave in depth coverage of both, the language and coding methodologies. This book is intended for: 1. College students. It is organized in 13 chapters, each covering a separate aspect of the language, with complete examples. All VHDL code described in the book is on a companion 3.5" PC disk. Students can compile and simulate the examples to get a greater understanding of the language. Each chapter includes a series of exercises to reinforce the concepts. 2. Engineers. It is written by an aerospace engineer who has 26 years of hardware, software, computer architecture and simulation experience. It covers practical applications ofVHDL with coding styles and methodologies that represent what is current in the industry. VHDL synthesizable constructs are identified. Guidelines for testbench designs are provided. Also included is a project for the design of a synthesizable Universal Asynchronous Receiver Transmitter (UART), and a testbench to verify proper operation of the UART in a realistic environment, with CPU interfaces and transmission line jitter. An introduction to VHDL Initiative Toward ASIC Libraries (VITAL) is also provided. The book emphasizes VHDL 1987 standard but provides guidelines for features implemented in VHDL 1993.

Product Details

ISBN-13: 9781461359784
Publisher: Springer US
Publication date: 04/19/2013
Edition description: Softcover reprint of the original 1st ed. 1995
Pages: 365
Product dimensions: 7.01(w) x 10.00(h) x 0.03(d)

Table of Contents

Preface
Chapter 1.0. VHDL Overview and Concepts
Chapter 2.0. Basic LanguageDrivers
Chapter 5.0. VHDL Timing
Chapter 6.0. Packages
Chapter 9.0. Design 12.0. UART Package Standard
Appendix C: Package Textio
Appendix D: STD_Logic_Textio
Appendix E: Package
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