Wafer-Level Testing and Test During Burn-in for Integrated Circuits

by Sudarshan Bahukudumbi, Krishnendu Chakrabarty

Overview

Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product costs in semiconductor manufacturing.

Engineers learn how to implement the testing of integrated circuits at the wafer level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.

Product Details

ISBN-13:	9781596939899
Publisher:	Artech House, Incorporated
Publication date:	02/28/2010
Series:	Artech House Integrated Microsystems
Pages:	215
Product dimensions:	6.10(w) x 9.20(h) x 0.70(d)

About the Author

Sudarshan Bahukudumbi is a quality and reliability test engineer at Intel Corporation. He has written several articles in peer-reviewed journals and is a frequent presenter at industry conferences.

Table of Contents

Preface xiii

Acknowledgments xv

Chapter 1 Introduction 1

1.1 Background 4

1.1.1 System-Level Design-for-Test and Test Scheduling for Core-Based SoCs 4

1.1.2 Wafer-Level Test During Burn-In 6

1.1.3 Scan Design 9

1.2 Key Drivers for Wafer-Level Test and Burn-In 9

1.2.1 Challenges Associated with Wafer Sort 10

1.2.2 Emergence of KGDs 11

1.2.3 WLTBI: Industry Adoption and Challenges 11

1.3 Wafer-Level Test Planning for Core-Based SoCs 16

1.4 Wafer-Level Defect Screening for Mixed-Signal SoCs 17

1.5 WLTBI of Core-Based SoCs 17

1.6 Power Management for WLTBI 18

1.7 How This Book Is Organized 18

References 20

Chapter 2 Wafer-Level Test and Burn-In Industry Practices and Trends 25

2.1 Overview and Definitions 25

2.2 Status of Wafer-Level Test and WLBI 29

2.2.1 Wafer-Level Burn-In 31

2.3 Doing Both Wafer-Level Test and Wafer-Level Burn-In 33

2.4 Practical Matters 34

2.4.1 Volumes Needed 34

2.4.2 Power per Die and per Wafer 36

2.4.3 Types of Die That Can Be Tested and Burned-In 36

2.4.4 Functional Tests Versus Parametric Tests 36

2.4.5 Number of Contacts per Die 37

2.4.6 Number of Signal Channels Needed 37

2.4.7 Single-Pass Versus Multiple Pass 38

2.4.8 Maximum Force per Wafer 38

2.4.9 Contact Method 39

2.4.10 Contact Life 40

2.4.11 Minimizing Costs for SDBs and Contactors 41

2.4.12 Bumped Wafers Versus Wafers with Bond Pads 41

2.4.13 Pitch 41

2.4.14 Pad Size 42

2.4.15 Coplanarity 43

2.4.16 Background (Thinned) Wafers and Plastic-Backed Wafers 43

2.4.17 More Than One Die Type on the Wafer 43

2.4.18 Changing Cartridges 43

2.4.19 Test Electronics 44

2.4.20 Die Power and Shorted Die 44

2.4.21 Current per Die and per Wafer 44

2.4.22 Voltage Levels Needed 45

2.4.23 Clock and Pattern Frequencies 45

2.4.24 Wafer Maps and Binning 45

2.5 Future Projections 45

References 46

Chapter 3 Resource-Constrained Testing of Core-Based SoCs 49

3.1 Defect Probability Estimation for Embedded Cores 51

3.1.1 Unified Negative-Binomial Model for Yield Estimation 51

3.1.2 Procedure to Determine Core Defect Probabilities 52

3.2 Test-Length Selection for Wafer-Level Test 56

3.2.1 Test-Length Selection Problem: $$$TLS 60

3.2.2 Efficient Heuristic Procedure 62

3.2.3 Greedy Heuristic Procedure 64

3.3 Experimental Results 65

3.3.1 Approximation Error in P^r_S Due to Taylor Series Approximation 68

3.4 Test Data Serialization 72

3.4.1 Test-Length and TAM Optimization Problem: $$$TLTWS 74

3.4.2 Experimental Results: $$$TLTWS 76

3.4.3 Enumeration-Based TAM Width and Test-Length Selection 80

3.4.4 TAM Width and Test-Length Selection Based on Geometric Programming 83

3.4.5 Approximation Error in P^r_S 87

3.5 Summary 88

References 89

Chapter 4 Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs 91

4.1 Test Wrapper for Analog Cores 92

4.1.1 Analog Test Wrapper Modes 94

4.2 Wafer-Level Defect Screening: Mixed-Signal Cores 94

4.2.1 Signature Analysis: Mean-Signature-Based Correlation (MSBC) 96

4.2.2 Signature Analysis: Golden-Signature-Based Correlation (GSBC) 97

4.3 Generic Cost Model 100

4.3.1 Correction Factors: Test Escapes and Yield Loss 100

4.3.2 Cost Model: Generic Framework 102

4.3.3 Overall Cost Components 103

4.4 Cost Model: Quantitative Analysis 104

4.4.1 Cost Model: Results for ASIC Chip K 105

4.4.2 Cost Model: Results Considering Failures Due to Both Digital and Mixed-Signal Cores 106

4.4.3 Cost Model: Results Considering Failure Distributions 108

4.5 Summary 113

4.6 Acknowledgments 114

References 114

Chapter 5 Wafer-Level Test During Burn-In: Test Scheduling for Core-Based SOCs 117

5.1 Cycle-Accurate Power Modeling 119

5.1.1 Transitions in a Scan Chain 120

5.1.2 Transitions in Wrapper Chains 124

5.2 Test Scheduling for WLTBI 125

5.2.1 Graph-Matching-Based Approach for Test Scheduling 126

5.3 Heuristic Procedure to Solve P_Core-Order 131

5.4 Baseline Methods 132

5.5 Experimental Results 132

5.6 Summary 139

5.7 Acknowledgments 139

References 139

Chapter 6 Wafer-Level Test During Bum-In: Power Management by Test-Pattern Ordering 141

6.1 Background: Cycle-Accurate Power Modeling 142

6.1.1 Scan-Chain Transition-Count Calculation 142

6.2 Test-Pattern Ordering Problem: P_TPO 144

6.2.1 Computational Complexity of _TPO 147

6.3 Heuristic Methods for Test-Pattern Ordering 148

6.4 Baseline Approaches 150

6.4.1 Baseline Method 1: Average Power Consumption 150

6.4.2 Baseline Method 2: Peak Power Consumption 151

6.5 Experimental Results 151

6.6 Summary 155

References 160

Chapter 7 Wafer-Level Test During Burn-In: Power Management by Test-Pattern Manipulation 163

7.1 Minimum-Variation X-Fill Problem: P_MVF 164

7.1.1 Metrics: Variation in Power Consumption During Test 164

7.1.2 Outline of Proposed Method 165

7.2 Framework to Control Power Variation for WLTBI 166

7.2.1 Minimum- Variation X -Filling 166

7.2.2 Eliminating Capture-Power Violations 169

7.2.3 Test-Pattern Ordering for WLTBI 170

7.2.4 Complete Procedure 171

7.3 Baseline Approaches 172

7.3.1 Baseline Method 1: Adjacent Fill 172

7.3.2 Baseline Method 2: 0-Fill 174

7.3.3 Baseline Method 3:1-Fill 174

7.3.4 Baseline Method 4: ATPG-Compacted Test Sets 174

7.4 Experimental Results 175

7.5 Summary 181

References 182

Chapter 8 Conclusions 183

8.1 Summary 183

8.2 Future Work 185

8.2.1 Integrated Test-Length and Test-Pattern Selection for Core-Based SoCs 185

8.2.2 Multiple Scan-Chain Design for WLTBI 186

8.2.3 Layout-Aware SoC Test Scheduling for WLTBI 186

References 187

List of Symbols 189

List of Acronyms 191

About the Authors 195

Index 197