Logic Synthesis and Verification Algorithms / Edition 1

by Gary D. Hachtel, Fabio Somenzi

Overview

This book blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. This publication serves as a textbook for upper-division and first year graduate students in electrical and computer engineering courses.

Product Details

ISBN-13:	9780387310046
Publisher:	Springer US
Publication date:	02/10/2006
Edition description:	1996
Pages:	564
Product dimensions:	6.10(w) x 9.25(h) x 0.36(d)

Table of Contents

I: Introduction.1. Introduction.2. A Quick Tour of Logic Synthesis with the Help of a Simple Example.- II: Two Level Logic Synthesis. 3. Boolean Algebras. 4. Synthesis of Two-Level Circuits. 5. Heuristic Minimization of Two-Level Circuits. 6. Binary Decision Diagrams (BDDs).- III: Models of Sequential Systems. 7. Models of Sequential Systems. 8. Synthesis and Verification of Finite State Machines. 9. Finite Automata. IV: Multilevel Logic Synthesis. 10. Multi-Level Logic Synthesis. 11. Multi-Level Minimization. 12. Automatic Test Generation for Combinational Circuits. 13. Technology Mapping. A. ASCII Codes. B. Supplementary Problems.- Bibliography.- Index.